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| = Electronic Design Automation =
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| Fedora Electronic Lab is Fedora's high-end hardware design and simulation platform. This platform provides different hardware design flows based on the semiconductor industry's current trend. FEL maps in '''three methodologies''' {'''design, simulation and verification'''} with opensource EDA software.
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| | | [[Category:Docs Project]] |
| FEL's website : http://chitlesh.fedorapeople.org/FEL/
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| | | [[Category:Documentation beats]] |
| The latest methodology included on FEL platform is the means for verifications and debugging for digital based designs.
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| The perl modules included for F11 brings a new methodology under the Fedora umbrella. This methodology is Verification together with possibilities for co-simulation based design and simulation. Fedora remains the sole linux distribution distributing FEL methodologies for hardware design, simulation and verification.
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| Updates of the existing RPM packages have improved design experience in terms of development time and debugging. While FEL understands Moore's Law is important for its userbase, these improvements will allow users to design a more efficient and successful designs with opensource software.
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| These enhancements brought to the Fedora umbrella increase chances that Fedora users can complete their high-end hardware design even if scaled to 90nm and wrap up their project with final tapeout.
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| FEL bridges 2 different opensource communities :
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| * opensource software community
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| * opensource hardware community
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| After 3 consecutive and successive releases, FEL/Fedora is regarded as the Leader in this field by both communities due to its 3-years experience and quality EDA solutions.
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| Below entails the highlights of the major development items to put the quality barrier higher than the previous releases:
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| * Perl modules to extend vhdl and verilog support. These perl modules together with rawhide's gtkwave improves chip testing support.
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| * Introduction of Verilog-AMS modeling into ngspice
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| * Improved VHDL debugging support with gcov.
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| * Improved support for re-usable HDL packages as IP core
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| * Improved PLI support on both iverilog and ghdl
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| * Introduction of C-based methodologies for HDL testbenches and models.
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| * Improved co-simulation based hardware design.
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| * Introduction of design tools for DSP design flow
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| Users who are using the standard fedora live media and even
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| yum groupinstall 'Electronic Lab'
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| to deploy this high-end hardware design, simulation and verification platform.
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| [[Category:Docs_Project]] | |
| [[Category:Documentation_beats]] | |
