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{{header|docs}}
{{header|docs}}
{{Docs_beat_open}}
{{Draft}}
= Circuit Design =
=== archimedes ===
=== drawtiming ===
=== emacs-vregs-mode ===
 
=== kicad ===
=== mot-adms ===
=== ngspice === 
tclspice-22-5.cvs20101113.fc15.i686 
=== pcb ===
=== perl-Verilog ===
perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch
                     
perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch                         
perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch                         
perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch                           
perl-ModelSim-List-0.06-6.fc15.noarch                               
perl-Perlilog-0.3-6.fc15.noarch                                     
perl-SystemC-Vregs-1.463-5.fc15.noarch                               
perl-SystemPerl-1.336-1.fc15.i686                                                                         
perl-Verilog-CodeGen-0.9.4-5.fc15.noarch                             
perl-Verilog-Readmem-0.04-5.fc15.noarch


{{Docs_beat_closed}}


[[Category:Docs Project]]
[[Category:Docs Project]]
[[Category:Draft documentation]]
[[Category:Draft documentation]]
[[Category:Documentation beats]]
[[Category:Documentation beats]]

Latest revision as of 01:31, 20 September 2016

Beat Closed on Wiki
Work on beats has now moved to git at https://pagure.io/fedora-docs/release-notes. If you have changes or additions, please contact the docs team via #fedora-docs, docs@lists.fedoraproject.org, or with the release-notes BZ component.
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