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| = Circuit Design =
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| === archimedes ===
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| Rebuild for F15 against GNU Archimedes release 0.9.1: no up-stream changes
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| http://www.gnu.org/software/archimedes/
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| === drawtiming ===
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| Rebuild for F15 against drawtiming release 0.7.1: no up-stream changes
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| http://drawtiming.sourceforge.net
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| === gtkwave ===
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| '''gtkwave''' is an analysis tool used to perform debugging on Verilog or VHDL simulation models.
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| With Fedora 15 '''gtkwave''' has been upgraded to 3.3.18, with improvements and new features respect to the release 3.3.10 present in Fedora 14. Among these there are:
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| additions of new tcl functions to enhance Tcl access; added support for process and transaction filters in MinGW and support for Open New Window to MinGW; in order to aid in indexing, detection for Verilog XL-style VCD identifiers in all vcd loaders in gtkwave. Updates to manual supporting GTKWave 3.3.18. For all details and fixes, view the CHANGELOG.TXT in the doc package.
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| http://gtkwave.sourceforge.net/
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| === kicad ===
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| (At now rebuilded against 2010.05.27-2363)
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| ??
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| '''kicad''' is a set of applications used to capture electronic schematics and design printed circuit boards. -->
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| With Fedora 15, '''kicad''' has been upgraded from 2010.05.27 to 2011.mm.dd. Among the new features: addition of a tool (bitmap2component) to create logos from .bmp bitmaps, vectored by potrace for no pixelation effect. In eeschema: addition of "template fieldnames"; netlist generation, changes the rule to calculate netnames of nets with labels; exporting of the generic netlist in XML. In gerbview: improved support to Gerber language; added in file dialog, multiple file selection; Draw mode selector (in left toolbar). For all details, view the [http://bazaar.launchpad.net/~kicad-testing-committers/kicad/testing/annotate/head%3A/CHANGELOG.txt CHANGELOG.TXT (rev.2794)].
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| https://launchpad.net/kicad
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| ??
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| === mot-adms ===
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| http://mot-adms.sourceforge.net/
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| === ngspice ===
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| http://ngspice.sourceforge.net
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| (tclspice-22-5.cvs20101113.fc15.i686)
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| === pcb ===
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| http://pcb.sourceforge.net
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| === perl-Verilog ===
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| http://www.veripool.org/wiki/verilog-perl
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| perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch
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| perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch
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| perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch
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| perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch
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| perl-ModelSim-List-0.06-6.fc15.noarch
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| perl-Perlilog-0.3-6.fc15.noarch
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| perl-SystemC-Vregs-1.463-5.fc15.noarch
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| perl-SystemPerl-1.336-1.fc15.i686
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| perl-Verilog-CodeGen-0.9.4-5.fc15.noarch
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| perl-Verilog-Readmem-0.04-5.fc15.noarch
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| | {{Docs_beat_closed}} |
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| [[Category:Docs Project]] | | [[Category:Docs Project]] |
| [[Category:Draft documentation]] | | [[Category:Draft documentation]] |
| [[Category:Documentation beats]] | | [[Category:Documentation beats]] |
