Revision as of 17:17, 2 February 2011

Beat is open
This beat is now ready to have Fedora 25 content added by the beat writer

This page is a draft only
It is still under construction and content may change. Do not rely on the information on this page.

Circuit Design

tclspice-22-5.cvs20101113.fc15.i686

perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch

perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch

perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch

perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch

perl-ModelSim-List-0.06-6.fc15.noarch

perl-Perlilog-0.3-6.fc15.noarch

perl-SystemC-Vregs-1.463-5.fc15.noarch

perl-SystemPerl-1.336-1.fc15.i686

perl-Verilog-CodeGen-0.9.4-5.fc15.noarch

perl-Verilog-Readmem-0.04-5.fc15.noarch

@@ Line 1: / Line 1: @@
 {{header|docs}}
 {{Docs_beat_open}}
+{{Draft}}
+= Circuit Design =
+=== archimedes ===
+=== drawtiming ===
+=== emacs-vregs-mode ===
+=== kicad ===
+=== mot-adms ===
+=== ngspice ===
+tclspice-22-5.cvs20101113.fc15.i686
+=== pcb ===
+=== perl-Verilog ===
+perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch
+perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch
+perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch
+perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch
+perl-ModelSim-List-0.06-6.fc15.noarch
+perl-Perlilog-0.3-6.fc15.noarch
+perl-SystemC-Vregs-1.463-5.fc15.noarch
+perl-SystemPerl-1.336-1.fc15.i686
+perl-Verilog-CodeGen-0.9.4-5.fc15.noarch
+perl-Verilog-Readmem-0.04-5.fc15.noarch