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* '''gnucap''': http://gnucap.org/gnucap-man-html/index.html
* '''gnucap''': http://gnucap.org/gnucap-man-html/index.html
* '''ngspice''': http://ngspice.sourceforge.net/docs.html
* '''ngspice''': http://ngspice.sourceforge.net/docs.html
* '''gspiceui''': User manual integrated in the application
* '''gspiceui''': http://gspiceui.sourceforge.net/ (User manual into the application)
* '''xcircuit schematic''': http://opencircuitdesign.com/xcircuit/
* '''xcircuit schematic''': http://opencircuitdesign.com/xcircuit/


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* '''GHDL''': http://ghdl.free.fr/manual.html
* '''GHDL''': http://ghdl.free.fr/manual.html
* '''Qucs''': http://qucs.sourceforge.net/docs.html
* '''Qucs''': http://qucs.sourceforge.net/docs.html
* '''FreeHDL''': http://www.freehdl.seul.org/ (man)  
* '''FreeHDL''': http://www.freehdl.seul.org/ (man page)  
* '''Icarus Verilog''': http://www.icarus.com/eda/verilog/ (man page)
* '''Icarus Verilog''': http://www.icarus.com/eda/verilog/ (man page)
* '''GTKWave''': http://gtkwave.sourceforge.net/ (man page)
* '''GTKWave''': http://gtkwave.sourceforge.net/ (man page)
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== RTL and logic synthesis design flows ==
== RTL and logic synthesis design flows ==
* '''pharosc''' (library): http://www.vlsitechnology.org/index.html (man page)
* '''Alliance''': http://www-asim.lip6.fr/recherche/alliance/doc/design-flow/index.html
* '''gds2pov''': http://www.atchoo.org/gds2pov/ (missing)
== Circuit and PCB Layout ==
* '''PCB''': http://pcb.gpleda.org/manual.html
* '''gerbv''': http://gerbv.gpleda.org/index.html (man page)
* '''gEDA''': http://geda.seul.org/wiki/
* '''kicad''': http://iut-tice.ujf-grenoble.fr/kicad/ (User manual into the application)
(...)

Revision as of 16:16, 24 July 2010

This page is a draft only
It is still under construction and content may change. Do not rely on the information on this page.

References to guides/tutorial of the tools that ship with FEL:

ASIC Analog Circuit Design and Simulation

ASIC Layout, DRC and LVS

Digital Simulation and Verification

RTL and logic synthesis design flows

Circuit and PCB Layout

(...)