Documentation Circuit Design Beat

Beat is open
This beat is now ready to have Fedora 25 content added by the beat writer

This page is a draft only
It is still under construction and content may change. Do not rely on the information on this page.

Circuit Design

archimedes

Rebuild for F15 against GNU Archimedes release 0.9.1: no up-stream changes

http://www.gnu.org/software/archimedes/

drawtiming

http://drawtiming.sourceforge.net

gtkwave

http://gtkwave.sourceforge.net/

kicad

https://launchpad.net/kicad

mot-adms

http://mot-adms.sourceforge.net/

ngspice

http://ngspice.sourceforge.net

(tclspice-22-5.cvs20101113.fc15.i686)

pcb

http://pcb.sourceforge.net

perl-Verilog

http://www.veripool.org/wiki/verilog-perl

perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch

perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch

perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch

perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch

perl-ModelSim-List-0.06-6.fc15.noarch

perl-Perlilog-0.3-6.fc15.noarch

perl-SystemC-Vregs-1.463-5.fc15.noarch

perl-SystemPerl-1.336-1.fc15.i686

perl-Verilog-CodeGen-0.9.4-5.fc15.noarch

perl-Verilog-Readmem-0.04-5.fc15.noarch