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;Big-endian{{Anchor|big-endian}} | ;Big-endian{{Anchor|big-endian}} | ||
:In the context of the ARM architecture, big-endian is defined as the memory organization in which: | :In the context of the ARM architecture, big-endian is defined as the memory organization in which: | ||
* a byte or halfword at a word-aligned address is the most significant byte or halfword at that address | :* a byte or halfword at a word-aligned address is the most significant byte or halfword at that address | ||
* a byte at a halfword-aligned address is the most significant byte in the halfword at that address. | :* a byte at a halfword-aligned address is the most significant byte in the halfword at that address. | ||
{{Anchor|C}} | {{Anchor|C}} | ||
== C == | == C == | ||
Revision as of 20:15, 2 April 2013
Glossary
This page will be used to document a list of terms and acronyms used in reference to the ARM Architecture
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
A
- Aarch64
- The ARMv8 64-bit execution state, that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 execution state provides a single instruction set, A64..
B
- Big-endian
- In the context of the ARM architecture, big-endian is defined as the memory organization in which:
- a byte or halfword at a word-aligned address is the most significant byte or halfword at that address
- a byte at a halfword-aligned address is the most significant byte in the halfword at that address.
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
